1. Field of the Invention
The present invention relates to a semiconductor device having a central processing unit (CPU); in particular, relates to an improvement thereof to ensure a hold time for a data signal.
2. Description of the Background Art
FIG. 19 is a block diagram showing a structure of a conventional semiconductor device as a background of the present invention. This conventional device 150 is formed as a microprocessor (MPU) comprising a CPU 91 or as a microcomputer (MCU) further comprising a peripheral circuit not shown in FIG. 19 in addition to the CPU 91.
The device 150 comprises a tri-state buffer 92 as well as the CPU 91. A data signal DI outputted by the CPU 91 is inputted to the tri-state buffer 92. The tri-state buffer 92 passes the data signal DI therethrough and outputs the same as a data signal DE when the control signal WR* is active (i.e. at an active level). Hereinafter, an expression xe2x80x9cX*xe2x80x9d represents that a signal X is low-active, i.e. active at low level. The tri-state buffer 92 sets the output thereof in high-impedance (electrically disconnected) state irrespective of the data signal DI when the control signal WR* is normal. Thus, the tri-state buffer 92 adjusts a timing of the output of the data signal DE transferred from the device 150 to an external device such as a memory device, according to the control signal WR* from the CPU 91.
The CPU 91 operates in synchronization with a clock signal CLK. The control signal WR*, therefore, undergoes transition between an active and a normal levels, being synchronized with the clock signal CLK. Accordingly, the data signal DE is outputted from the device 150 to the external device synchronously with the clock signal CLK. FIG. 20 is a timing diagram illustrating this operation.
The clock signal CLK rises up at respective times T1 to T4. The data signal having a value xe2x80x9cZxe2x80x9d is outputted from the CPU 91 during two cycles of the clock signal CLK from the time T1 to T3. During this period, the control signal WR* changes from a normal level to an active level at the time T2 when the clock signal CLK rises up, and returns to the normal level at the time T3 when the clock signal CLK rises up next. As a result, the value xe2x80x9cZxe2x80x9d is outputted as the data signal DE from the time T2 to T3.
Thus, the output of the value xe2x80x9cZxe2x80x9d in the data signal DE starts and ends in synchronization with the clock signal CLK. On the other hand, since the external device such as a memory device receiving the data signal DE also operates synchronously with the control signal WR*, it is disadvantageously hard to use an external device to be connected with the device 150 which requires a sufficiently long hold time for the data signal DE.
The following documents are known to disclose techniques merely relating to the control of a clock signal: Japanese Patent Laying Open Gazette No. 1-265351, No. 8-123717, No. 2-100750, No. 9-319704, No. 8-6896, No. 6-291615, No. 9-128333, No. 5-257886, No. 62-281047, No. 4-294442, No. 2-171907, and No. 4-370862.
A first aspect of the present invention is directed to a semiconductor device. The semiconductor device comprises: a CPU operating in synchronization with an internal clock signal; a terminal, being exposed outside said semiconductor device so as to be connectable with a delay circuit which delays said internal clock signal for a predetermined delay time and thereby outputs a delayed signal as a delay clock signal, for receiving said delay clock; and a data transfer control circuit for relaying a data signal transferred between said CPU and an external device with a delay for said delay time according to said delay clock signal supplied through said terminal.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the data transfer control circuit comprises: a data hold circuit for holding the data signal, which is inputted to the data transfer control circuit, in synchronization with the delay clock signal; a buffer control circuit for outputting a first control signal, being active during a period delayed for the delay time behind a period during which the data signal is inputted, according to a second control signal, which the CPU outputs in synchronization with the internal clock to inform the buffer control circuit that a transfer of the data signal is started and ended, and to the delay clock signal; and a tri-state buffer for outputting the data signal held by the data hold circuit to an outside of the data transfer control circuit only when the first control signal is active.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the data transfer control circuit further comprises a selection circuit, interposed between the buffer control circuit and the tri-state buffer, for selectively transferring either the first control signal or a third control signal which the CPU outputs to inform the external device that the data signal is transferred, to the tri-state buffer according to a selection signal.
According to a fourth aspect of the present invention, in the semiconductor device of the first or second aspect, the semiconductor device further comprises a tri-state buffer for relaying another data signal transferred between the CPU and another external device, and the tri-state buffer passes the another data signal therethrough only when a control signal, which the CPU outputs to inform the another external device that the another data signal is transferred, is active.
According to a fifth aspect of the present invention, in the semiconductor device of any one of the first to fourth aspects, the semiconductor device further comprises the delay circuit, the delay circuit is connected with the terminal, and the delay time is set shorter than one cycle of the internal clock.
In the device of the first aspect, since the data transfer control circuit relays a data signal transferred between the CPU and the external device with a delay, a hold time can be ensured for the data signal. Moreover, it is possible to set the delay time variously depending on the condition under which the semiconductor device is used after the semiconductor device is completed as a product because the terminal exposed outside is connectable with the delay circuit.
In the device of the second aspect, the data transfer control circuit is most simply formed of the data hold circuit, the tri-state buffer and the buffer control circuit.
In the device of the third aspect, since the tri-state buffer is selectively controlled by either of the two control signals through the selection circuit, it is possible to select a hold time depending on the characteristics of the connected external device.
In the device of the fourth aspect, since the two paths having different hold times are provided for transferring the data signals, external devices having different characteristics in relation to the hold time are connectable even simultaneously.
In the device of the fourth aspect, since the delay circuit is already provided, a user can use the device without attaching a delay circuit. Moreover, since the delay time is set shorter than one cycle of the internal clock signal, there is no apprehension that an erroneous data signal is transferred between the CPU and the external device.
Accordingly, it is an object of the present invention to obtain a semiconductor device capable of ensuring the hold time sufficiently long for the data signal transferred between the CPU and the external device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.